The customer wants to test the design of their ASIC devices. To test their IC, they need to stimulate the IC with a particular bit-pattern many times. They call each pattern period a "view". During each view, they need to collect data from the IC. The IC is not purely digital, so the IC output data is not the same for each view, although the stimulus pattern is the same for each view. The stimulus pattern must be "real-time" during a view, but there can be arbitrary delay or dead-time between views. They want to use the dead-time to send the collected data from a view to a file on the PC. This will reduce the on-board memory required for the entire sequence of views. With the above scheme, each collected view of data will be appended to a single PC file.
They wish to use a pattern-generator to generate stimulus to test their ASIC and then capture the response from their ASIC. The stimulus definition exists as an ASCII file with rows and columns of 1s and 0s. The columns are one for each input pin of the ASIC and the rows are one for each time tic (every 50 ns). They wish to record the digital response from the separate output pins of their ASIC as another ASCII file of 1s and 0s. Again, every clock-tic generates another row, and each output pin has an associated column. The stimulus is independent of the response. (There is no feedback from the response to alter the stimulus). The IC will be mounted on a test board that can have the proper connectors for interfacing with a digital data-acquisition device and a digital pattern-generator.
They have the following concerns:
1.) They want to ensure that they have the proper input and output logic levels on the connectors that go to or come from our boards. Their test board generates and responds to 0-3.3 V signals via a level-shifting buffer. This buffer IC can drive 24 mA loads.
2.) Their test board generates a 20 MHz clock. They need to ensure that the data acquisition device samples the test board outputs at an appropriate time-delay relative to the pattern-generator output times.
They want a minimum of modification or work on the front-end.
A Windows C/C++ application is required to control, record, display, and save the data to a disk-file.
The CompuGen 3250 digital pattern generator and the complementary CompuScope 3200 digital acquisition board combine to provide a perfect solution to the customer's requirement.
They would excite their chip with the CG3250 and get back the response with the CS3200. Their concern was that their 0-3.3V CMOS coming from the FPGA would not drive the 50W load presented by inputs of the CS3200. Therefore, they need the GaGe CMOS Buffer Board. The buffer board is used to boost up all signals to a sufficient level in order to drive 50W.
Since both the CG3250 and the CS3200 must be clocked by the customer's 20 MHz reference clock, they require the external clock upgrade for the CG3250. The external clock input is a standard feature on the CS3200.
In addition, a GaGe BNC Breakout Board will make the initial testing much easier, since the digital signals can be directly observed on an analog oscilloscope.
They will stimulate their ASIC with the CG3250 and then capture the output with the CS3200 and compare. Initially GaGeBit, GaGe's stand-alone logic-analyzer-like application, will suffice as the interface software. They will need (32-bit) conversion utilities such as "ASC2GS32.EXE" and the sample-program "Gbit2Txt.c" in order to convert GaGe SIG file, required by GaGeBit, to and from ASCII text. They will need extra cables, as each setup will take two cables each. Ultimately, an SDK would be necessary in order to automate the testing.
GaGe's CompuScope CS3200 and CompuGen CG3250 provides both the necessary flexibility and the fast bus-transfer speeds.
The normal mode-of-operation of GaGe cards is called Memory-Mode. As an example of the Memory-Mode of operation for CompuGens, to transfer a 1,024 point x 32-bit-wide pattern from PC-RAM using the ISA-bus transfer-speeds (at about 1 MB/s), then that would take about 4,096 microseconds. At the CG3250 conversion-rate of 20 MS/s (i.e. 50 nanoseconds per clock-tic), this 1,024 point pattern would take about 204ms to output. A nominal 100ms is required to rearm the card for the next trigger. This gives a total upload-time of 4.4 milliseconds.
Using the CS3200 in Memory-Mode, acquiring a single record of 1,024 point x 32-bit-wide at the same 20 MS/s would again take about 204ms. Using the much-faster PCI bus-mastered transfer-rates of over 100 MB/s, transferring the resulting 1,024*4 = 4 KB (since four bytes per sample-point) from the card into the PC-RAM would only take about 41ms. Rearming the cards to prepare for the next trigger takes about 30ms per card. Therefore, allowing for a healthy safety-margin, this entire capture cycle will probably take less than 0.5ms.
Accordingly, GaGe recommended the minimum on-board memory depth of 2 MegaBytes. The stimulation-pattern can be uploaded once into the CG3250. Between repeated scans, all the data points for one record are offloaded from the CS3200 across the PCI-bus into PC-RAM.
The customer was easily able to incorporate the sample-programs from the CompuScope and CompuGen Software Development Kits into their existing Windows application. These sample-programs are intentionally simplified for easy transfer into any given software application.
The combination of GaGe's superior hardware and powerful software products enabled the customer to quickly move from a preliminary prototype to a fully-commercialized diagnostic system.
We encourage you to contact us and discuss your test & measurement application in more detail with our engineering team. GaGe can provide tailored custom data acquisition hardware and software solutions to meet specific application requirements: